Subranging analog-to-digital converters (also known as residue converters) are well known in the art, as shown by U.S. Pat. Nos. 3,597,761, 3,956,746, 4,550,309 and 4,733,217.
U.S. Pat. No. 4,550,309 shows a residue converter in which resolution is enhanced by introducing a random dither signal into the process. Referring to FIG. 1, the apparatus 10 disclosed in U.S. Pat. No. 4,500,309 includes a sample and hold circuit 12, first pass and second pass scaling circuits 14, 16, an 8-bit analog-to-digital (ADC) converter 18, a digital-to-analog converter (DAC) 20, an analog difference circuit 22, a 13-bit accumulator 24, and a 13-bit latch 26. To these foregoing elements (which are conventional in any subranging converter) are added a digital noise source 28, a second 13-bit accumulator 30, and a second 13-bit latch 32.
In operation, the converter 10 operates by first scaling an analog input signal by a factor of K in scaling circuit 14. The scaled analog input signal is then converted into a first pass 8-bit digital word approximately corresponding thereto by the ADC 18. The first pass output from ADC 18 is loaded into the 8 most significant bits of the 13-bit second accumulator 30. A 6-bit digital noise word from noise source 28 is loaded into the least significant bits of this accumulator, forming a one-bit overlap with the ADC output word. The composite, accumulated value of these data words is latched by the latch circuit 32 and loaded into the output accumulator 24.
The accumulated word latched into the latch 32 is converted into analog form by the DAC 20. This analog signal is subtracted from the input analog signal by the analog subtraction circuit 22. The result of this subtraction, termed an analog residue signal, is provided to the second pass scaling circuit 16.
In the second pass conversion, the 8-bit output word from the ADC 18 corresponding to the scaled residue signal is loaded into the 8 least significant bits of the output accumulator 24 and accumulated with the 13-bit composite word that was loaded during the first pass. The dither component of the composite word is an error term that is reflected (negatively) in the analog residue signal converted in the second pass. The second pass conversion, when accumulated with the first pass composite word, thus operates to cancel the dither error. The output from the accumulator 24 is latched by the latch circuit 26 and provides the final digital output signal.
In the illustrated system, the first pass scaling circuit 14 has a gain K of 0.125. The second pass scaling circuit 16 has a gain L of 4. Thus, it will be recognized that the analog signal applied to the ADC 18 in the second pass is amplified by a factor of 32 relative to the first pass. This yields five additional bits of conversion resolution and three bits of overlap. (Overlap refers to the fact that the second pass 8-bit output of the ADC 18 is shifted 5 bits from the first pass output to provide 13-bit "resolution" or sensitivity of the final output digital signal representing the input analog signal.) The three least significant bits of the first pass conversion thus overlap and are combined with the three most significant bits of the second pass conversion. (Of course, the five most significant bits of the first pass conversion may also be affected if there is carryover from combining overlapped bits.)
The manner by which the dithering operation improves the overall ADC linearity may be understood by assuming that an input signal varies slowly in the vicinity of a value for which the ADC exhibits a significant jump or discontinuity. That is, the ADC produces a value which differs by a full bit from the previous signal. Further, the ADC may exhibit hysteresis, i.e., successive conversions from slowly increasing signals may not match those from slowly decreasing signals. Dithering reduces the deleterious effect of such ADC anomalies by producing, for a given value of input signal, a sequence of conversions derived from a neighborhood around that signal value. Particular conversion errors are thus randomized. Erroneous conversions from ADC anomalies may then be averaged with correct conversions, and the effect of the anomalies is diluted.
The amount of error that can be corrected by dither is related to the amount of overlap between the first and second pass conversions. As noted, the ADC 18 resolves eight bits, so the overlap between passes is three bits. That is, the lower three bits of the first pass conversion have the same weight as the upper three bits of the second pass conversion. Another way of interpreting this is that the magnification in the second pass conversion is 32 (the ratio between the gain of the second scaling circuit 16 to the gain of the first scaling circuit 18), or the equivalent of a 5-bit shift in position (rather than eight, which would be the case if there were no overlap). Due to this overlap, the second pass conversion can resolve errors in the first pass of up to eight times (three bits of position--the overlap) the weight of the least significant bit of the first pass. This overlap permits the error reducing dither signal to be introduced.
Another way of looking at the second pass conversion and its overlap is that the first pass conversion (which is loaded into the DAC 20 for the second pass) contains inaccuracies. These can be errors in the first pass conversion, but in the case of dither, they are deliberately added. If the DAC 20 is highly linear, the second pass conversion resolves the inaccuracies and they subtract in the final accumulator 24 (the sign through the DAC signal path is negative). The amount of overlap determines the size of errors, including dither, that can be tolerated in the first pass conversion.
To increase resolution, the obvious solution is reduce the overlap. This requires that the dither also be reduced, reducing the performance advantages it offers. Alternatively, the resolution of both the ADC 18 and the DAC 20 could be increased.
To obtain 16 bit resolution (instead of 13), the overlap would have to be reduced to zero, entirely eliminating the dither and error correction.
It is interesting to note that in the FIG. 1 system, each bit of the dither word has a direct effect on the output from ADC 18 in the second pass conversion. Taking the most extreme example, the least significant bit of the dither word is the 13th (and least significant) bit of the composite signal latched by the latch 32. This signal is converted into analog form by converter 20. When this analog output signal is converted into a residue signal, it is, as noted earlier, amplified by a factor of 32 or 2.sup.5, relative to the first pass. This gain causes the least significant bit of the 13-bit composite word (the noise LSB) effectively to be shifted 5 bits to the left. In so doing, it becomes the least significant bit of the 8-bit second pass data word output by the ADC 18. Put another way, a change in the least significant bit of the digital noise word is reflected as a change in the least significant bit of ADC 18 in the second pass conversion word produced by the ADC 18.
In a converter according to the present invention, the preceding is not the case. One or more of the least significant bits of the digital noise word are of such fine bit-resolution that, even after scaling, they are still not large enough to always change the least significant bit of the ADC 18 when producing the second pass conversion.
While such an extension of the original dithering technology is counter intuitive and may seem to have no effect, in fact it has an advantageous effect. Namely, the 13th bit of converter resolution statistically varies between one and zero in accordance with these additional bits of resolution that are not directly reflected in the output of ADC 18. By this arrangement, additional resolution is achieved without sacrificing the advantageous error correction afforded by overlap.
The foregoing and additional features and advantages of the present invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.